I am working at AMD (Advanced Micro Devices) as a senior design engineer from May 2024 onwards. My work focuses on Performance Analysis, Modeling and RTL Correlation for the Last level caches and interconnects.

Prior to this, I was part of the Multicore Architecture Research Systems (MARS) Lab, under the supervision of Dr. John Jose and Dr. T. Venkatesh . My broader area of research lies in Computer Systems Architecture and Design. My Ph.D work specifically focused on "Design, Analysis and Optimization of Large-Scale Disaggregated Memory Systems for Data Centers". As part of my PhD work, I developed an open-source Cycle-Level Architectural Simulator framework DRackSim for experimentation of large scale CXL-based Pooled Memory Systems. Here is the link to github Repo.

Apart from this, I also explored Chiplet-based IMC accelerators and had been working on few research problems with my lab-mate. Currently, I am interested to work in intersection of CXL and AI, specifically to counter memory bottlenecks.